1. Field of the Invention
The present invention relates to a high-performance semiconductor device and a method for producing the same.
2. Description of the Related Art
Recently in the field of CMOS semiconductor devices, more and more devices have adopted a triple-well structure, in which a deep well is added to the conventional twin-well structure (see, for example, technical Report of Mitsubishi Electric Corporation, Vol. 68, No. 3, pp. 7-10, 1994). The triple-well structure has been adopted in order to include two or more types of substrate potentials together in an n-well and a p-well, respectively, in one chip. An exemplary known method for producing the triple-well structure is shown in FIGS. 6A through 6E.
Specifically, as shown in FIG. 6A, first a LOCOS isolation layer 42 is formed on one of two main surfaces of a p-type semiconductor substrate 41 (also referred to simply as the "substrate 41"). Next, as shown in FIG. 6B, a resist mask 43 is formed on a prescribed area of the one main surface of the p-type semiconductor substrate 41 including the LOCOS isolation layer 42 at the corresponding positions. Then, P.sup.+ (phosphorus ions) is implanted into the substrate 41 at a high acceleration energy using the mask 43, thereby forming an n-well 44 at a deep position in the substrate 41.
Then, the resist mask 43 is removed, and a different resist mask 45 is formed to cover a prescribed area of the one main surface of the substrate 41. Using the mask 45, B.sup.+ (boron ions) is implanted into the substrate 41, thereby forming a first p-well 46 in the substrate 41 so as to be in contact with the deep n-well 44. By the same implantation of B.sup.+, a second p-well 47 is formed in an area where the first p-well 46 is not formed, as shown in FIG. 6C. By further performing ion implantation under different conditions using the same mask 45 again, a punch-through stopper layer and a threshold voltage control layer (neither is shown in FIG. 6C) for a first n-channel MOS transistor having a deep substrate potential are formed inside the first p-well 46.
After the resist mask 45 is removed, still another resist mask 48 is formed on areas corresponding to the areas where the first p-well 46 and the second p-well 47 are formed. Using the mask 48, P.sup.+ is implanted into the substrate 41, thereby forming an n-well 49 as shown in FIG. 6D. By further performing ion implantation under different conditions using the same mask 48 again, a punch-through stopper layer and a threshold voltage control layer (neither is shown in FIG. 6D) for a p-channel MOS transistor are formed inside the n-well 49.
Next, after the resist mask 48 is removed, still another resist mask 50 is formed in an area corresponding to an area excluding the area where the second p-well 47 is formed, as shown in FIG. 6E. Using the mask 50, B.sup.+ is implanted into the substrate 41, whereby a punch-through stopper layer and a threshold voltage control layer (neither is shown in FIG. 6E) for a second n-channel MOS transistor having a shallow substrate potential are formed inside the second p-well 47.
The above-described conventional method for producing the triple-well structure includes additional two more mask processes, compared to the method for producing the conventional twin-well structure. Since the mask process generally involves the steps of coating, patterning and removing the masks, such additional two more mask processes tend to cause significant increase in time and cost for production.